To program a standalone CPLD like this one, a dedicated programmer is needed. An approved “Altera USB Blaster” costs $50 and is available from places like Digikey. I have several clones that I ...

Using an external MCU as a crude clock source for the Altera CPLD. (Credit: [Doug Brown]) One exciting feature of hardware development involving MCUs and FPGAs is that you all too often need ...

Intel is likely to start the process by selling its programmable chip unit Altera. Intel has already told investors that there will be an IPO for Altera to enhance its fortunes. Intel also wants ...

Two months after Intel spun off the Programmable Solutions Group into a stand-alone FPGA company, it reveals it’s taking its original Altera name and chasing a market opportunity exceeding $55 ...

Depending on the CPLD, the combinatorial logic function supports from four to sixteen product terms with wide fan-in. Complex programmable logic devices also vary in terms of logic gates and shift ...

The plan will include ideas on how to shave overall costs by selling businesses, including its programmable chip unit Altera, that Intel can no longer afford to fund from the company’s once ...

Unlike Xilinx, Altera provides the maximum number of equivalent MACs for ... Chang Choo, "Designing LMS FIR Filters Using CPLD," Proc. ICSPAT-2000, Dallas, Texas, Oct. 16-19, 2000. B. Widrow and S.D.

September 27, 2012 – Altera Corporation (Nasdaq: ALTR) today announced availability of its Cyclone V GX FPGA development kit based on the industry’s lowest-power, lowest-cost 28 nm FPGA. Altera was ...

You will learn how to describe the difference between an FPGA, a CPLD, an ASSP, and an ASIC ... You will learn the steps in the standard FPGA design flow, how to use Intel Altera’s Quartus Prime ...

Macrocells: Macrocells on most modern SPLDs or CPLDs contain sum-of-product combinatorial logic function and an optional flip-flop. The combinatorial logic function typically supports four to sixteen ...